TrenchFETs are a class of metal oxide semiconductor (MOS) devices wherein the channel between the source and drain of the device runs vertically, under the control of a gate electrode. The gate electrode is accommodated in a trench within the device and isolated from the semiconductor layers typically by gate oxide lining the side-walls and base of the trench.
Such devices typically have an n-type source region adjacent the surface of the device, beneath which lies a p-type body region (which accommodates the channel). Beneath the p-type body region is the n-type drain region. A trench in the device, the side walls of which are lined with gate oxide, provides access for the gate electrode to the body region, in order to provide a channel within the body region. In operation, application of a potential to the gate electrode opens the channel in the body region and allows electrical conduction between the source and drain regions.
The design of all TrenchFETs incorporate an area of trench where the gate electrode is exposed to the drain. Where the gate electrode is exposed to the drain a gate/drain capacitor is formed. The magnitude of the gate/drain capacitance is dependent upon the area of the gate exposed. For fast switching devices it is beneficial to reduce the gate/drain capacitance as much as possible for the following reasons: firstly, to reduce the switching loss per cycle; secondly, to reduce the total gate charge, and thirdly to improve the gate's immunity by maximising the reverse breakdown parameter (BVdso).
One method of reducing the gate/drain capacitance is the RESURF (REduced SURface Field) stepped oxide concept. A schematic representation of such a device is shown in FIG. 1.
FIG. 1 depicts part of a semiconductor device having source region 1 and drain region 2 between which is a body region 3. Typically source region 1 and drain region 2 are n-type semiconductor, and body region 3 is p-type semiconductor. The device is characterised by a trench, generally depicted by 4, which extends from the top surface into the device, through the source region and body region and into the drain region. The trench is lined with oxide adjacent to the side walls 5 and 6 and the bottom 7. The upper part of the trench is filled with gate electrode 8. The gate electrode 8 typically comprises polysilicon material. Deeper in the trench than the gate electrode 8, and electrically isolated from it, is a further region typically of polysilicon material, designated as shield electrode 9. As depicted in FIG. 1, the shield electrode generally lies further from the side walls of the trench, than does the gate electrode. The shield electrode, which is electrically isolated from the gate electrode but typically connected to the source electrode, has the effect of shielding the gate electrode from the drain region. However, this is only effective if the distance between the body/drain junction and the bottom of the gate electrode is small, as is apparent from FIG. 1. As the distance increases the level of shielding provided by the shield electrode reduces.
There is therefore an ongoing need for a TrenchFET which provides the benefit of the RESURF stepped oxide concept, but does not suffer from the close tolerances involved in aligning the bottom of the gate electrode with the body/drain junction.